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% " %$ " "!" ! july 2001 digital audio products data manual slws106c
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2001, texas instruments incorporated
iii contents section title page 1 introduction 1?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 features 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 functional block diagram 1 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 terminal assignments 1 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 1 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 terminal functions 1 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 specifications 2?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 absolute maximum ratings over operating free-air temperature range 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 recommended operating conditions 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 electrical characteristics over recommended operating conditions 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 adc 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 dac 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 analog line input to line output 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . 2.3.4 stereo headphone output 2 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 analog reference levels 2 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 digital i/o 2 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.7 supply current 2 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 digital-interface timing 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 audio interface (master mode) 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 audio interface (slave-mode) 2 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 three-wire control interface 2 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 two-wire control interface 2 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 how to use the aic23 3?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 control interfaces 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 spi 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 i2c 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 register map 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 analog interface 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 line inputs 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 microphone input 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 line outputs 3 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 headphone output 3 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 analog bypass mode 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 sidetone insertion 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv 3.3 digital audio interface 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 digital audio-interface modes 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 audio sampling rates 3 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 digital filter characteristics 3 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . a mechanical data a ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v list of illustrations figure title page 2 ? 1 system-clock timing requirements 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 master-mode timing requirements 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 slave-mode timing requirements 2 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 three-wire control interface timing requirements 2 ? 7 . . . . . . . . . . . . . . . . . . . . 2 ? 5 two-wire control interface timing requirements 2 ? 7 . . . . . . . . . . . . . . . . . . . . . 3 ? 1 spi timing 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 2-wire i2c compatible timing 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 analog line input circuit 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 microphone input circuit 3 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 right-justified mode timing 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 left-justified mode timing 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7i 2 s mode timing 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 dsp mode timing 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9 digital de-emphasis filter response ? 441 khz sampling 3 ? 12 . . . . . . . . . . . . . 3 ? 10 digital de-emphasis filter response ? 48 khz sampling 3 ? 12 . . . . . . . . . . . . . 3 ? 11 adc digital filter response i: ti dsp and normal modes (group delay = 12 output samples) 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 12 adc digital filter ripple i: ti dsp and normal modes (group delay = 20 output samples) 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 13 adc digital filter response ii: ti dsp mode only 3 ? 14 . . . . . . . . . . . . . . . . . . . 3 ? 14 adc digital filter ripple ii: ti dsp mode only 3 ? 14 . . . . . . . . . . . . . . . . . . . . . . 3 ? 15 adc digital filter response iii: ti dsp and normal modes (group delay = 3 output samples) 3 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 16 adc digital filter ripple iii: ti dsp and normal modes 3 ? 15 . . . . . . . . . . . . . . . 3 ? 17 adc digital filter response iv: ti dsp mode only 3 ? 16 . . . . . . . . . . . . . . . . . . 3 ? 18 adc digital filter ripple iv: ti dsp mode only 3 ? 16 . . . . . . . . . . . . . . . . . . . . . . 3 ? 19 dac digital filter response i: ti dsp and normal modes 3 ? 17 . . . . . . . . . . . . 3 ? 20 dac digital filter ripple i: ti dsp and normal modes 3 ? 17 . . . . . . . . . . . . . . . . 3 ? 21 dac digital filter response ii: ti dsp mode only 3 ? 18 . . . . . . . . . . . . . . . . . . . 3 ? 22 dac digital filter ripple ii: ti dsp mode only 3 ? 18 . . . . . . . . . . . . . . . . . . . . . . 3 ? 23 dac digital filter response iii: ti dsp and normal modes 3 ? 19 . . . . . . . . . . . 3 ? 24 dac digital filter ripple iii: ti dsp and normal modes 3 ? 19 . . . . . . . . . . . . . . . 3 ? 25 dac digital filter response iv: ti dsp mode only 3 ? 20 . . . . . . . . . . . . . . . . . . 3 ? 26 dac digital filter ripple iv: ti dsp mode only 3 ? 20 . . . . . . . . . . . . . . . . . . . . . .
vi
1 ? 1 1 introduction the tlv320aic23 is a high-performance stereo audio codec with highly integrated analog functionality. the analog-to-digital converters (adcs) and digital-to-analog converters (dacs) within the tlv320aic23 use multibit sigma-delta technology with integrated oversampling digital interpolation filters. data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 khz to 96 khz, are supported. the adc sigma-delta modulator features third-order multibit architecture with up to 90-dba signal-to-noise ratio (snr) at audio sampling rates up to 96 khz, enabling high-fidelity audio recording in a compact, power-saving design. the dac sigma-delta modulator features a second-order multibit architecture with up to 100-dba snr at audio sampling rates up to 96 khz, enabling high-quality digital audio-playback capability, while consuming less than 23 mw during playback only. the tlv320aic23 is the ideal analog input/output (i/o) choice for portable digital audio-player and recorder applications, such as mp3 digital audio players. integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone amplifier, with analog volume control and mute, and a complete electret-microphone-capsule biasing and buffering solution. the headphone amplifier is capable of delivering 30 mw per channel into 32 ? . the analog bypass path allows use of the stereo-line inputs and the headphone amplifier with analog volume control, while completely bypassing the codec, thus enabling further design flexibility, such as integrated fm tuners. a microphone bias-voltage output provides a low-noise current source for electret-capsule biasing. the aic23 has an integrated adjustable microphone amplifier (gain adjustable from 1 to 5) and a programmable gain microphone amplifier (0 db or 20 db). the microphone signal can be mixed with the output signals if a sidetone is required. while the tlv320aic23 supports the industry-standard oversampling rates of 256 f s and 384 f s , unique oversampling rates of 250 f s and 272 f s are provided, which optimize interface considerations in designs using ti c54x digital signal processors (dsps) and universal serial bus (usb) data interfaces. a single 12-mhz crystal can supply clocking to the dsp, usb, and codec. the tlv320aic23 features an internal oscillator that, when connected to a 12-mhz external crystal, provides a system clock to the dsp and other peripherals at either 12 mhz or 6 mhz, using an internal clock buffer and selectable divider. audio sample rates of 48 khz and compact-disc (cd) standard 44.1 khz are supported directly from a 12-mhz master clock with 250 f s and 272 f s oversampling rates. low power consumption and flexible power management allow selective shutdown of codec functions, thus extending battery life in portable applications. this design solution, coupled with the industry ? s smallest package, the ti proprietary microstar junior ? using only 25 mm 2 of board area, makes powerful portable stereo audio designs easily realizable in a cost-effective, space-saving total analog i/o solution: the tlv320aic23. 1.1 features ? high-performance stereo codec ? 90-db snr multibit sigma-delta adc (a-weighted at 48 khz) ? 100-db snr multibit sigma-delta dac (a-weighted at 48 khz) ? 1.42 v ? 3.6 v core digital supply: compatible with ti c54x dsp core voltages ? 2.7 v ? 3.6 v buffer and analog supply: compatible both ti c54x dsp buffer voltages ? 8-khz ? 96-khz sampling-frequency support ? software control via ti mcbsp-compatible multiprotocol serial port ? i 2 c-compatible and spi-compatible serial-port protocols ? glueless interface to ti mcbsps ? audio-data input/output via ti mcbsp-compatible programmable audio interface ? i 2 s-compatible interface requiring only one mcbsp for both adc and dac ? standard i 2 s, msb, or lsb justified-data transfers ? 16/20/24/32-bit word lengths microstar junior is a trademark of texas instruments.
1 ? 2 ? audio master/slave timing capability optimized for ti dsps (250/272 f s ), usb mode ? industry-standard master/slave support provided also (256/384 f s ), normal mode ? glueless interface to ti mcbsps ? integrated total electret-microphone biasing and buffering solution ? low-noise micbias pin at 3/4 avdd for biasing of electret capsules ? integrated buffer amplifier with tunable fixed gain of 1 to 5 ? additional control-register selectable buffer gain of 0 db or 20 db ? stereo-line inputs ? integrated programmable gain amplifier ? analog bypass path of codec ? adc multiplexed input for stereo-line inputs and microphone ? stereo-line outputs ? analog stereo mixer for dac and analog bypass path ? analog volume control with mute ? highly efficient linear headphone amplifier ? 30 mw into 32 ? from a 3.3-v analog supply voltage ? flexible power management under total software control ? 23-mw power consumption during playback mode ? standby power consumption <150 w ? power-down power consumption <15 w ? industry ? s smallest package: 32-pin ti proprietary microstar junior ? ? 25 mm 2 total board area ? 28-pin tssop also is available (62 mm 2 total board area) ? ideally suitable for portable solid-state audio players and recorders
1 ? 3 1.2 functional block diagram control interface digital filters digital audio interface ? ? dac 6 to ? 73 db, 1 db steps headphone driver ? ? dac 6 to ? 73 db, 1 db steps headphone driver clkout divider (1x, 1/2x) osc cs sdin sclk mode dvdd bvdd dgnd lrcin din lrcout dout bclk avdd vmid agnd rlinein llinein hpvdd hpgnd rhpout rout lout lhpout xti/mclk xto clkout dspcodec tlv320aic23 1.0x 1.0x vadc vmid 50 k ? 50 k ? ? ? adc 2:1 mux vdac ? ? adc 2:1 mux mute, 0 db, 20 db vmid 50 k ? 10 k ? vadc 12 to ? 34.5 db, 1.5 db steps 1.0x 1.5x vdac 12 to ? 34 db, 1.5 db steps micbias micin clkin divider (1x, 1/2x) line mute line mute side tone mute bypass mute bypass mute note: mclk, bclk, and sclk are all asynchronous to each other.
1 ? 4 1.3 terminal assignments lrcin nc 123456789 25 24 23 22 21 20 19 18 17 10 11 12 13 14 15 16 32 31 30 29 28 27 26 dout lrcout hpvdd lhpout rhpout hpgnd xti/mclk sclk sdin mode cs llinein rlinein lout rout avdd agnd vmid micbias micin nc nc din bclk clkout bvdd dgnd dvdd xto nc gqe package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 bvdd clkout bclk din lrcin dout lrcout hpvdd lhpout rhpout hpgnd lout rout avdd dgnd dvdd xto xti/mclk sclk sdin mode cs llinein rlinein micin micbias vmid agnd pw package (top view) nc ? no internal connection 1.4 ordering information package t a 32-pin microstar junior gqe 28-pin tssop pw ? 10 c to 70 c tlv320aic23gqe tlv320aic23pw ? 40 c to 85 c tlv320aic23igqe TLV320AIC23IPW
1 ? 5 1.5 terminal functions terminal name no. i/o description name gqe pw i/o agnd 5 15 analog supply return avdd 4 14 analog supply input. voltage level is 3.3 v nominal. bclk 23 3 i/o i 2 s serial-bit clock. in audio master mode, the aic23 generates this signal and sends it to the dsp. in audio slave mode, the signal is generated by the dsp. bvdd 21 1 buffer supply input. voltage range is from 2.7 v to 3.6 v. clkout 22 2 o clock output. this is a buffered version of the xti input and is available in 1x or 1/2x frequencies of xti. bit 07 in the sample rate control register controls frequency selection. cs 12 21 i control port input latch/address select. for spi control mode this input acts as the data latch control. for i 2 c control mode this input defines the seventh bit in the device address field. see section 3.1 for details. din 24 4 i i 2 s format serial data input to the sigma-delta stereo dac dgnd 20 28 digital supply return dout 27 6 o i 2 s format serial data output from the sigma-delta stereo adc dvdd 19 27 digital supply input. voltage range is 3.3 v nominal. hpgnd 32 11 analog headphone amplifier supply return hpvdd 29 8 analog headphone amplifier supply input. voltage level is 3.3 v nominal. lhpout 30 9 o left stereo mixer-channel amplified headphone output. nominal 0-db output level is 1 v rms . gain of ? 73 db to 6 db is provided in 1-db steps. llinein 11 20 i left stereo-line input channel. nominal 0-db input level is 1 v rms . gain of ? 34.5 db to 12 db is provided in 1.5-db steps. lout 2 12 o left stereo mixer-channel line output. nominal output level is 1.0 v rms . lrcin 26 5 i/o i 2 s dac-word clock signal. in audio master mode, the aic23 generates this framing signal and sends it to the dsp. in audio slave mode, the signal is generated by the dsp. lrcout 28 7 i/o i 2 s adc-word clock signal. in audio master mode, the aic23 generates this framing signal and sends it to the dsp. in audio slave mode, the signal is generated by the dsp. micbias 7 17 o buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. voltage level is 3/4 avdd nominal. micin 8 18 i buffered amplifier input suitable for use with electret-microphone capsules. without external resistors a default gain of 5 is provided. see section 2.3.1.2 for details. mode 13 22 i serial-interface-mode input. see section 3.1 for details. nc 1, 9 17, 25 not used ? no internal connection rhpout 31 10 o right stereo mixer-channel amplified headphone output. nominal 0-db output level is 1 v rms . gain of ? 73 db to 6 db is provided in 1-db steps. rlinein 10 19 i right stereo-line input channel. nominal 0-db input level is 1 v rms . gain of ? 34.5 db to 12 db is provided in 1.5-db steps. rout 3 13 o right stereo mixer-channel line output. nominal output level is 1.0 v rms . sclk 15 24 i control-port serial-data clock. for spi and i 2 c control modes this is the serial-clock input. see section 3.1 for details. sdin 14 23 i control-port serial-data input. for spi and i 2 c control modes this is the serial-data input and also is used to select the control protocol after reset. see section 3.1 for details. vmid 6 16 i midrail voltage decoupling input. 10- f and 0.1- f capacitors should be connected in parallel to this terminal for noise filtering. voltage level is 1/2 avdd nominal. xti/mclk 16 25 i crystal or external-clock input. used for derivation of all internal clocks on the aic23. xto 18 26 o crystal output. connect to external crystal for applications where the aic23 is the audio timing master. not used in applications where external clock source is used.
1 ? 6
2 ? 1 2 specifications 2.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, av dd to agnd, dv dd to dgnd, bv dd to dgnd, hpv dd to hpgnd (see note 1) ? 0.3 v to + 3.63 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog supply return to digital supply return, agnd to dgnd ? 0.3 v to + 3 .63 v . . . . . . . . . . . . . . . . . . . . . . . input voltage range, all input signals: digital ? 0.3 v to dv dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog ? 0.3 v to av dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . case temperature for 10 seconds 240 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a ? 10 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: dv dd may not exceed bv dd + 0.3v; bv dd may not exceed av dd + 0.3v or hpv dd + 0.3. 2.2 recommended operating conditions min nom max unit analog supply voltage, av dd , hpv dd (see note 2) 2.7 3.3 3.6 v digital buffer supply voltage, bv dd (see note 2) 2.7 3.3 3.6 v digital core supply voltage, dv dd (see note 2) 1.42 1.5 3.6 v analog input voltage, full scale ? 0db (av dd = 3.3 v) 1 v rms stereo-line output load resistance 10 k ? headphone-amplifier output load resistance 0 ? clkout digital output load capacitance 20 pf all other digital output load capacitance 10 pf stereo-line output load capacitance 50 pf xti master clock input 18.43 mhz adc or dac conversion rate 96 khz operating free-air temperature, t a ? 10 70 c note 2: digital voltage values are with respect to dgnd; analog voltage values are with respect to agnd.
2 ? 2 2.3 electrical characteristics over recommended operating conditions, av dd , hpv dd , bv dd = 3.3 v, dv dd = 1.5 v, slave mode, xti/mclk = 256fs, f s = 48 khz (unless otherwise stated) 2.3.1 adc 2.3.1.1 line input to adc parameter test conditions min typ max unit input signal level (0 db) 1 v rms si g nal-to-noise ratio, a-wei g hted, 0-db g ain (see notes 3 f s = 48 khz (3.3 v) 85 90 db g,g,g( and 4) f s = 48 khz (2.7 v) 90 db dynamic ran g e, a-wei g hted, ? 60-db full-scale input (see av dd = 3.3 v 85 90 db yg,g, ( note 4) av dd = 2.7 v 90 db total harmonic distortion 1dbin p ut 0 db gain av dd = 3.3 v ? 80 db total harmonic distortion , ? 1 - db input , 0 - db gain av dd = 2.7 v 80 db power supply rejection ratio 1 khz, 100 mv pp 50 db adc channel separation 1 khz input tone 90 db programmable gain 1 khz input tone, r source < 50 ? ? 34.5 12 db programmable gain step size monotonic 1.5 db mute attenuation 0 db, 1 khz input tone 80 db in p ut resistance 12 db input gain 10 20 k ? ? ? source impedance, see section 1.2, functional block diagram ) parameter test conditions min typ max unit input signal level (0 db) 1.0 v rms signal to noise ratio a weighted 0 db gain (see notes 3 and 4) av dd = 3.3 v 80 85 db signal - to - noise ratio , a - weighted , 0 - db gain (see notes 3 and 4) av dd = 2.7 v 84 db dynamic range a weighted 60 db full scale in p ut (see note 4) av dd = 3.3 v 80 85 db dynamic range , a - weighted , ? 60 - db full - scale input (see note 4) av dd = 2.7 v 84 db total harmonic distortion 1dbin p ut 0 db gain av dd = 3.3 v ? 60 db total harmonic distortion , ? 1 - db input , 0 - db gain av dd = 2.7 v ? 60 db power supply rejection ratio 1 khz, 100 mv pp 50 db programmable gain boost 1 khz input tone, r source < 50 ? 20 db microphone-path gain micboost = 0, r source < 50 ? 14 db mute attenuation 0 db, 1 khz input tone 60 80 db input resistance 8 14 k ? input capacitance 10 pf notes: 3. ratio of output level with 1-khz full-scale input, to the output level with the input short circuited, measured a-weigh ted over a 20-hz to 20-khz bandwidth using an audio analyzer. 4. all performance measurements done with 20-khz low-pass filter and, where noted, a-weighted filter. failure to use such a filt er results in higher thd + n and lower snr and dynamic range readings than shown in the electrical characteristics. the low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2 ? 3 2.3.1.3 microphone bias parameter test conditions min typ max unit bias voltage 3/4 avdd ? 100 m 3/4 avdd 3/4 avdd + 100 m v bias-current source 3 ma output noise voltage 1 khz to 20 khz 25 nv/ hz 2.3.2 dac 2.3.2.1 line output, load = 10 k ? , 50 pf parameter test conditions min typ max unit 0-db full-scale output voltage (ffffff) 1.0 v rms signal to noise ratio a weighted 0 db gain (see notes 3 4 and 5) av dd = 3.3 v f s = 48khz 90 100 db signal - to - noise ratio , a - weighted , 0 - db gain (see notes 3 , 4 , and 5) av dd = 2.7 v f s = 48 khz 100 db dynamic range a weighted (see note 4) av dd = 3.3 v 85 90 db dynamic range , a - weighted (see note 4) av dd = 2.7 v tbd db av dd =33v 1 khz, 0 db ? 88 ? 80 db total harmonic distortion av dd = 3 . 3 v 1 khz, ? 3 db ? 92 ? 86 db total harmonic distortion av dd =27v 1 khz, 0 db ? 85 db av dd = 2 . 7 v 1 khz, ? 3 db ? 88 db power supply rejection ratio 1 khz, 100 mv pp 50 db dac channel separation 100 db notes: 3. ratio of output level with 1-khz full-scale input, to the output level with the input short circuited, measured a-weigh ted over a 20-hz to 20-khz bandwidth using an audio analyzer. 4. all performance measurements done with 20-khz low-pass filter and, where noted, a-weighted filter. failure to use such a filt er results in higher thd + n and lower snr and dynamic range readings than shown in the electrical characteristics. the low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 5. ratio of output level with 1-khz full-scale input, to the output level with all zeros into the digital input, measured a-weig hted over a 20-hz to 20-khz bandwidth. 2.3.3 analog line input to line output (bypass) parameter test conditions min typ max unit 0-db full-scale output voltage 1.0 v rms signal to noise ratio a weighted 0 db gain (see notes 3 and 4) av dd = 3.3 v 90 95 db signal - to - noise ratio , a - weighted , 0 - db gain (see notes 3 and 4) av dd = 2.7 v 95 db av dd =33v 1 khz, 0 db ? 86 ? 80 db total harmonic distortion av dd = 3 . 3 v 1 khz, ? 3 db ? 92 ? 86 db total harmonic distortion av dd =27v 1 khz, 0 db ? 86 db av dd = 2 . 7 v 1 khz, ? 3 db ? 92 db power supply rejection ratio 1 khz, 100 mv pp 50 db dac channel separation (left to right) 1 khz, 0 db 80 db notes: 3. ratio of output level with 1-khz full-scale input, to the output level with the input short circuited, measured a-weigh ted over a 20-hz to 20-khz bandwidth using an audio analyzer. 4. all performance measurements done with 20-khz low-pass filter and, where noted, a-weighted filter. failure to use such a filt er results in higher thd + n and lower snr and dynamic range readings than shown in the electrical characteristics. the low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2 ? 4 2.3.4 stereo headphone output parameter test conditions min typ max unit 0-db full-scale output voltage 1.0 v rms maximum output power, p o r l = 32 ? 30 mw r l = 16 ? 40 mw signal-to-noise ratio, a-weighted (see note 4) av dd = 3.3 v 90 97 db total harmonic distortion av dd = 3.3 v, p o = 10 mw 0.1 % total harmonic distortion dd , 1 khz output p o = 20 mw 1.0 % power supply rejection ratio 1 khz, 100 mv pp 50 db programmable gain 1 khz output ? 73 6 db programmable-gain step size 1 db mute attenuation 1 khz output 80 db note 4: all performance measurements done with 20-khz low-pass filter and, where noted, a-weighted filter. failure to use such a filter results in higher thd + n and lower snr and dynamic range readings than shown in the electrical characteristics. the low-pass filter re moves out-of-band noise, which, although not audible, may affect dynamic specification values. 2.3.5 analog reference levels parameter min typ max unit reference voltage avdd/2 ? 50 mv avdd/2 + 50 mv v divider resistance 40 50 60 k ? 2.3.6 digital i/o parameter min typ max unit v il input low level 0.3 bv dd v v ih input high level 0.7 bv dd v v ol output low level 0.1 bv dd v v oh output high level 0.9 bv dd v 2.3.7 supply current parameter min typ max unit record and playback (all active) 23 record and playback (osc, clk, and mic output powered down) 18 tt l l t line playback only 7 i tot total supply current, no in p ut signal record only 13 ma no in ut signal analog bypass (line in to line out) 4 power down oscillator enabled 1.5 power down oscillator disabled 0.01
2 ? 5 2.4 digital-interface timing parameter min typ max unit t w(1) system clock p ulse duration mclk/xti high 18 ns t w(2) system - clock pulse duration , mclk/xti low 18 ns t c(1) system-clock period, mclk/xti 54 ns duty cycle, mclk/xti 40/60% 60/40% t pd(1) propagation delay, clkout 0 10 ns t c(1) t w(1) t w(2) t pd(1) mclk/xti clkout clkout (div 2) figure 2 ? 1. system-clock timing requirements 2.4.1 audio interface (master mode) parameter min typ max unit t pd(2) propagation delay, lrcin/lrcout 0 10 ns t pd(3) propagation delay, dout 0 10 ns t su(1) setup time, din 10 ns t h(1) hold time, din 10 ns bclk lrcin din t pd(2) t su(1) t h(1) t pd(3) dout lrcout figure 2 ? 2. master-mode timing requirements
2 ? 6 2.4.2 audio interface (slave-mode) parameter min typ max unit t w(3) pulse duration bclk high 20 ns t w(4) pulse duration , bclk low 20 ns t c(2) clock period, bclk 50 ns t pd(4) propagation delay, dout 0 10 ns t su(2) setup time, din 10 ns t h(2) hold time, din 10 ns t su(3) setup time, lrcin 10 ns t h(3) hold time, lrcin 10 ns bclk lrcin din t c(2) t w(4) t w(3) t su(3) t h(3) t su(2) t h(2) dout t pd(2) lrcout figure 2 ? 3. slave-mode timing requirements
2 ? 7 2.4.3 three-wire control interface (sdin) parameter min typ max unit t w(5) clock p ulse duration sclk high 20 ns t w(6) clock pulse duration , sclk low 20 ns t c(3) clock period, sclk 80 ns t su(4) clock rising edge to cs rising edge, sclk 60 ns t su(5) setup time, sdin to sclk 20 ns t h(4) hold time, sclk to sdin 20 ns t w(7) pulse duration cs high 20 ns t w(8) pulse duration , cs low 20 ns lsb t w(8) t c(3) t w(6) t w(5) t su(4) t h(4) t su(5) cs sclk din figure 2 ? 4. three-wire control interface timing requirements 2.4.4 two-wire control interface (i2c) parameter min typ max unit t w(9) clock p ulse duration sclk high 1.3 s t w(10) clock pulse duration , sclk low 600 ns f(sf) clock frequency, sclk 0 400 khz t h(5) hold time (start condition) 600 ns t su(6) setup time (start condition) 600 ns t h(6) data hold time 900 ns t su(7) data setup time 100 ns t r rise time, sdin, sclk 300 ns t f fall time, sdin, sclk 300 ns t su(8) setup time (stop condition) 600 ns sclk din t w(9) t w(10) t h(5) t h(6) t su(7) t su(8) figure 2 ? 5. two-wire control interface timing requirements
2 ? 8
3 ? 1 3 how to use the tlv320aic23 3.1 control interfaces the tlv320aic23 has many programmable features. the control interface is used to program the registers of the device. the control interface complies with spi (three-wire operation) and i 2 c (two-wire operation) specifications. the state of the mode terminal selects the control interface type. the mode pin must be hardwired to the required level. mode interface 0 i 2 c 1 spi 3.1.1 spi in spi mode, sdin carries the serial data, sclk is the serial clock and cs latches the data word into the tlv320aic23. the interface is compatible with microcontrollers and dsps with an spi interface. a control word consists of 16 bits, starting with the msb. the data bits are latched on the rising edge of sclk. a rising edge on cs after the 16th rising clock edge latches the data word into the aic (see figure 3-1). the control word is divided into two parts. the first part is the address block, the second part is the data block: b[15:9] control address bits b[8:0] control data bits b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ??????????????????? ??????????????????? msb lsb cs sclk sdin figure 3 ? 1. spi timing 3.1.2 i 2 c in i 2 c mode, the data transfer uses sdin for the serial data and sclk for the serial clock. the start condition is a falling edge on sdin while sclk is high. the seven bits following the start condition determine which device on the i 2 c bus receives the data. r/w determines the direction of the data transfer. the tlv320aic23 is a write only device and responds only if r/w is 0. the device operates only as a slave device whose address is selected by setting the state of the cs pin as follows. cs state (default = 0) address 0 0011010 1 0011011
3 ? 2 the device that recognizes the address responds by pulling sdin low during the ninth clock cycle, acknowledging the data transfer. the control follows in the next two eight-bit blocks. the stop condition after the data transfer is a rising edge on sdin when sclk is high (see figure 3-2). the 16-bit control word is divided into two parts. the first part is the address block, the second part is the data block: b[15:9] control address bits b[8:0] control data bits sclk sdi addr r/w ack b15 ? b8 ack b7 ? b0 ack start stop 1 78 9 1 89 18 9 figure 3 ? 2. 2-wire i 2 c compatible timing 3.1.3 register map the tlv320aic23 has the following set of registers, which are used to program the modes of operation. address register 0000000 left line input channel volume control 0000001 right line input channel volume control 0000010 left channel headphone volume control 0000011 right channel headphone volume control 0000100 analog audio path control 0000101 digital audio path control 0000110 power down control 0000111 digital audio interface format 0001000 sample rate control 0001001 digital interface activation 0001111 reset register left line input channel volume control (address: 0000000) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function lrs lim x x liv4 liv3 liv2 liv1 liv0 default 0 1 0 0 1 0 1 1 1 lrs left/right line simultaneous volume/mute update simultaneous update 0 = disabled 1 = enabled lim left line input mute 0 = normal 1 = muted liv[4:0] left line input volume control (10111 = 0 db default) 11111 = +12 db down to 00000 = ? 34.5 db in 1.5-db steps x reserved
3 ? 3 right line input channel volume control (address: 0000001) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function rls rim x x riv4 riv3 riv2 riv1 riv0 default 0 1 0 0 1 0 1 1 1 rls right/left line simultaneous volume/mute update simultaneous update 0 = disabled 1 = enabled rim right line input mute 0 = normal 1 = muted riv[4:0] right line input volume control (10111 = 0 db default) 11111 = +12 db down to 00000 = ? 34.5 db in 1.5-db steps x reserved left channel headphone volume control (address: 0000010) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function lrs lzc lhv6 lhv5 lhv4 lhv3 lhv2 lhv1 lhv0 default 0 1 1 1 1 1 0 0 1 lrs left/right headphone channel simultaneous volume/mute update simultaneous update 0 = disabled 1 = enabled lzc left-channel zero-cross detect zero-cross detect 0 = off 1 = on lhv[6:0] left headphone volume control (1111001 = 0 db default) 1111111 = +6 db down to 0000000 = ? 73 db in 1-db steps right channel headphone volume control (address: 0000011) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function rls rzc rhv6 rhv5 rhv4 rhv3 rhv2 rhv1 rhv0 default 0 1 1 1 1 1 0 0 1 rls right/left headphone channel simultaneous volume/mute update simultaneous update 0 = disabled 1 = enabled rzc right-channel zero-cross detect zero-cross detect 0 = off 1 = on rhv[6:0] right headphone volume control (1111001 = 0 db default) 1111111 = +6 db down to 0000000 = ? 73 db in 1-db steps analog audio path control (address: 0000100) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function x sta1 sta0 ste dac byp insel micm micb default 0 0 0 0 1 0 0 1 0 sta[1:0] sidetone attenuation 00 = ? 6 db 01 = ? 9 db 10 = ? 12 db 11 = ? 15 db ste sidetone enable 0 = disabled 1 = enabled dac dac select 0 = dac off 1 = dac selected byp bypass 0 = disabled 1 = enabled insel input select for adc 0 = line 1 = microphone micm microphone mute 0 = normal 1 = muted micb microphone boost 0=odb 1 = 20db x reserved
3 ? 4 digital audio path control (address: 0000101) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function x x x x x dacm deemp1 deemp0 adchp default 0 0 0 0 0 0 1 0 0 dacm dac soft mute 0 = disabled 1 = enabled deemp[1:0] de-emphasis control 00 = disabled 01 = 32 khz 10 = 44.1 khz 11 = 48 khz adchp adc high-pass filter 0 = disabled 1 = enabled x reserved power down control (address: 0000110) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function x off clk osc out dac adc mic line default 1 0 0 0 0 0 1 1 1 off device power 0 = on 1 = off clk clock 0 = on 1 = off osc oscillator 0 = on 1 = off out outputs 0 = on 1 = off dac dac 0 = on 1 = off adc adc 0 = on 1 = off mic microphone input 0 = on 1 = off line line input 0 = on 1 = off x reserved digital audio interface format (address: 0000111) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function x x ms lrswap lrp iwl1 iwl0 for1 for0 default 0 0 0 0 0 0 0 0 1 ms master/slave mode 0 = slave 1 = master lrswap dac left/right swap 0 = disabled 1 = enabled lrp dac left/right phase 0 = right channel on, lrcin high 1 = right channel on, lrcin low dsp mode 1 = msb is available on 2nd bclk rising edge after lrcin rising edge 0 = msb is available on 1st bclk rising edge after lrcin rising edge iwl[1:0] input bit length 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit for[1:0] data format 11 = dsp format, frame sync followed by two data words 10 = i 2 s format, msb first, left ? 1 aligned 01 = msb first, left aligned 00 = msb first, right aligned x reserved notes: 1. in master mode, the tlv320aic23 supplies the bclk, lrcout, and lrcin. in slave mode, bclk, lrcout, and lrcin are supplied to the tlv320aic23. 2. in master mode, bclk = mclk/4 for all sample rates except for 88.2 khz and 96 khz. for 88.2 khz and 96 khz sample rate, bclk = mclk. sample rate control (address: 0001000) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function x clkout clkin sr3 sr2 sr1 sr0 bosr usb/normal default 0 0 0 1 0 0 0 0 0 clkin clock input divider 0 = mclk 1 = mclk/2 clkout clock output divider 0 = mclk 1 = mclk/2
3 ? 5 sr[3:0] sampling rate control (see sections 3.3.2.1 and 3.3.2.2) bosr base oversampling rate usb mode: 0 = 250 f s 1 = 272 f s normal mode: 0 = 256 f s 1 = 384 f s usb/normal clock mode select: 0 = normal 1 = usb x reserved digital interface activation (address: 0001001) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function x x x x x x x x act default 0 0 0 0 0 0 0 0 1 act activate interface 0 = inactive 1 = active x reserved reset register (address: 0001111) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function res res res res res res res res res default 0 0 0 0 0 0 0 0 0 res write 000000000 to this register triggers reset 3.2 analog interface 3.2.1 line inputs the tlv320aic23 has line inputs for the left and the right audio channels (rlinein and llinein). both line inputs have independently programmable volume controls and mutes. active and passive filters for the two channels prevent high frequencies from folding back into the audio band. the line-input gain is logarithmically adjustable from 12 db to ? 34.5 db in 1.5-db steps. the adc full-scale range is 1.0 v rms at av dd = 3.3 v. the full-scale range tracks linearly with analog supply voltage av dd . to avoid distortions, it is important not to exceed the full-scale range. the gain is independently programmable on both left and right line-inputs. to reduce the number of software write cycles required. both channels can be locked to the same value by setting the rls and lrs bits (see section 3.1.3). the line inputs are biased internally to vmid. when the line inputs are muted or the device is set to standby mode, the line inputs are kept biased to vmid using special antithump circuitry. this reduces audible clicks that otherwise might be heard when reactivating the inputs. for interfacing to a cd system, the line input should be scaled to 1 v rms to avoid clipping, using the circuit shown in figure 3-3. r 2 r1 c1 c2 + cdin linein agnd where: r1 = 5 k ? r2 = 5 k ? c1 = 47 pf c2 = 470 nf figure 3 ? 3. analog line input circuit r1 and r2 divide the input signal by two, reducing the 2 v rms from the cd player to the nominal 1 v rms of the aic23 inputs. c1 filters high-frequency noise, and c2 removes any dc component from the signal. 3.2.2 microphone input micin is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. it has a programmable volume control and a mute function. active and passive filters prevent high frequencies from folding back into the audio band.
3 ? 6 the micin signal path has two gain stages. the first stage has a nominal gain of g1 = 50 k/10 k = 5. by adding an external resistor (r mic ) in series with micin, the gain of the first stage can be adjusted by g1 = 50 k/(10 k + r mic ). for example, r mic = 40 k gives a gain of 0 db. the second stage has a software programmable gain of 0 db or 20 db (see section 3.1.3). 50 k ? 10 k ? vmid 0 db/20 db to adc micin figure 3 ? 4. microphone input circuit the microphone input is biased internally to vmid. when the line inputs are muted, the micin input is kept biased to vmid using special antithump circuitry. this reduces audible clicks that may otherwise be heard when reactivating the input. the micbias output provides a low-noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. the maximum source current capability is 3 ma. this limits the smallest value of external biasing resistors that safely can be used. the micbias output is not active in standby mode. 3.2.3 line outputs the tlv320aic23 has two low-impedance line outputs (llineout and rlineout) capable of driving line loads with 10-k ? and 50-pf impedances. the dac full-scale output voltage is 1.0 v rms at av dd = 3.3 v. the full-scale range tracks linearly with the analog supply voltage av dd. the dac is connected to the line outputs via a low-pass filter that removes out-of-band components. no further external filtering is required in most applications. the dac outputs, line inputs, and the microphone signal are summed into the line outputs. these sources can be switched off independently. for example, in bypass mode, the line inputs are routed to the line outputs, bypassing the adc and the dac. if sidetone is enabled, the microphone signal is routed to both line outputs via a four-step programmable attenuation circuit. the line outputs are muted by either muting the dac (analog) or soft muting (digital) and disabling the bypass and sidetone paths (see section 3.1.3). 3.2.4 headphone output the tlv320aic23 has stereo headphone outputs (lhpout and rhpout), and is designed to drive 16- ? or 32- ? headphones. the headphone output includes a high-quality volume control and mute function. the headphone volume is logarithmically adjustable from 6 db to ? 73 db in 1-db steps. writing 000000 to the volume-control registers (see section 3.1.3) mutes the headphone output. when the headphone output is muted or the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks. a zero-cross detection circuit is provided under the control of the lzc and rzc bits. if this circuit is enabled, the volume-control values are updated only when the input signal to the gain stage is close to the analog ground level. this minimizes audible clicks as the volume is changed or the device is muted. this circuit has no time-out, so, if only dc levels are being applied to the gain stage input of more than 20 mv, the gain is not updated. the gain is independently programmable on the left and right channels. both channels can be locked to the same value by setting the rls and lrs bits (see section 3.1.3).
3 ? 7 3.2.5 analog bypass mode the tlv320aic23 includes a bypass mode in which the analog line inputs are directly routed to the analog line outputs, bypassing the adc and dac. this is enabled by selecting the bypass bit in the analog audio path control register[see section 3.1.3). for a true bypass mode, the output from the dac and the sidetone should be disabled. the line input and headphone output volume controls and mutes are still operational in bypass mode. therefore the line inputs, dac output, and microphone input can be summed together. the maximum signal at any point in the bypass path must be no greater than 1.0v rms at av dd =3.3v to avoid clipping and distortion. this amplitude tracks linearly with av dd . 3.2.6 sidetone insertion the tlv320aic23 has a sidetone insertion made where the microphone input is routed to the line and headphone outputs. this is useful for telephony and headset applications. the attenuation of the sidetone signal may be set to ? 6 db, ? 9 db, ? 12 db, or ? 1 db, by software selection (see section 3.1.3). if this mode is used to sum the microphone input with the dac output and line inputs, care must be taken not to exceed signal level to avoid clipping and distortion. 3.3 digital audio interface 3.3.1 digital audio-interface modes the tlv320aic23 supports four audio-interface modes. ? right justified ? left justified ? i 2 s mode ? dsp mode the four modes are msb first and operate with a variable word width between 16 to 32 bits (except right-justified mode, which does not support 32 bits). the digital audio interface consists of clock signal bclk, data signals din and dout, and synchronization signals lrcin and lrcout. bclk is an output in master mode and an input in slave mode. 3.3.1.1 right-justified mode in right-justified mode, the lsb is available on the rising edge of bclk, preceding a falling edge on lrcin or lrcout (see figure 3-5). lrcin/ bclk din/ n n ? 1 0 1 n ? 1 n 1/fs left channel right channel 1 0 0 msb lsb lrcout dout figure 3 ? 5. right-justified mode timing 3.3.1.2 left-justified mode in left-justified mode, the msb is available on the rising edge of bclk, following a rising edge on lrcin or lrcout (see figure 3-6)
3 ? 8 lrcin/ bclk din/ n n ? 1 0 1 n ? 1 n 1/fs left channel right channel 1 0 n msb lsb lrcout dout figure 3 ? 6. left-justified mode timing 3.3.1.3 i 2 s mode in i 2 s mode, the msb is available on the second rising edge of bclk, after the falling edge on lrcin or lrcout (see figure 3-7). lrcin/ bclk din/ n n ? 1 0 1 n ? 1 n 1/fs left channel right channel 1 0 msb lsb 1bclk lrcout dout figure 3 ? 7. i 2 s mode timing 3.3.1.4 dsp mode the dsp mode is compatible with the mcbsp ports of ti dsps. lrcin and lrcout must be connected to the frame sync signal of the mcbsp. a falling edge on lrcin or lrcout starts the data transfer. the left-channel data consists of the first data word, which is immediately followed by the right channel data word (see figure 3-8). input word length is defined by the iwl register. figure 3 ? 8 shows lrp = 1 (default lrp = 0). lrcin/ bclk din/ n n ? 1 0 1 n ? 1 n left channel right channel 1 0 msb lsb msb lsb lrcout dout figure 3 ? 8. dsp mode timing
3 ? 9 3.3.2 audio sampling rates the tlv320aic23 can operate in master or slave clock mode. in the master mode, the tlv320aic23 clock and sampling rates are derived from a 12-mhz mclk signal. this 12-mhz clock signal is compatible with the usb specification. the tlv320aic23 can be used directly in a usb system. in the slave mode, an appropriate mclk or crystal frequency and the sample rate control register settings control the tlv320aic23 clock and sampling rates. the settings in the sample rate control register control the clock mode and sampling rates. sample rate control (address: 0001000) bit d8 d7 d6 d5 d4 d3 d2 d1 d0 function x clkout clkin sr3 sr2 sr1 sr0 bosr usb/nor- mal default 0 0 0 0 0 0 0 0 0 clkout clock output divider 0 = mclk 1 = mclk/2 clkin clock input divider 0 = mclk 1 = mclk/2 sr[3:0] sampling rate control (see sections 3.3.2.1 and 3.3.2.2) bosr base oversampling rate usb mode: 0 = 250 f s 1 = 272 f s normal mode: 0 = 256 f s 1 = 384 f s usb/normal clock mode select: 0 = normal 1 = usb x reserved the clock circuit of the aic23 has two internal dividers. the first, controlled by clkin, applies to the sampling-rate generator of the codec. the second, controlled by clkout, applies only to the clkout terminal. by setting clkin to 1, the entire codec is clocked with half the frequency, effectively dividing the resulting sampling rates by two. the following sampling-rate tables are based on clkin = mclk. 3.3.2.1 usb-mode sampling rates (mclk = 12 mhz) in the usb mode, the following adc and dac sampling rates are available: sampling rate ? sampling - rate control settings adc dac filter type sampling rate control settings adc (khz) dac (khz) filter type sr3 sr2 sr1 sr0 bosr 96 96 3 0 1 1 1 0 88.2 88.2 2 1 1 1 1 1 48 48 0 0 0 0 0 0 44.1 44.1 1 1 0 0 0 1 32 32 0 0 1 1 0 0 8.021 8.021 1 1 0 1 1 1 8 8 0 0 0 1 1 0 48 8 0 0 0 0 1 0 44.1 8.021 1 1 0 0 1 1 8 48 0 0 0 1 0 0 8.021 44.1 1 1 0 1 0 1 ? the sampling rates are derived from the 12-mhz master clock. the available oversampling rates do not produce exactly 8-khz, 44. 1-khz, and 88.2-khz sampling rates, but 8.021 khz, 44.117 khz, and 88.235 khz, respectively. see figures 3 ? 17 through 3 ? 34 for filter responses
3 ? 10 3.3.2.2 normal-mode sampling rates in normal mode, the following adc and dac sampling rates, depending on the mclk frequency, are available: mclk = 12.288 mhz sampling rate sampling - rate control settings adc dac filter type sampling rate control settings adc (khz) dac (khz) filter type sr3 sr2 sr1 sr0 bosr 96 96 2 0 1 1 1 0 48 48 1 0 0 0 0 0 32 32 1 0 1 1 0 0 8 8 1 0 0 1 1 0 48 8 1 0 0 0 1 0 8 48 1 0 0 1 0 0 mclk = 11.2896 mhz sampling rate sampling - rate control settings adc dac filter type sampling rate control settings adc (khz) dac (khz) filter type sr3 sr2 sr1 sr0 bosr 88.2 88.2 2 1 1 1 1 0 44.1 44.1 1 1 0 0 0 0 8.021 8.021 1 1 0 1 1 0 44.1 8.021 1 1 0 0 1 0 8.021 44.1 1 1 0 1 0 0 mclk = 18.432 mhz sampling rate sampling - rate control settings adc dac filter type sampling rate control settings adc (khz) dac (khz) filter type sr3 sr2 sr1 sr0 bosr 96 96 2 0 1 1 1 1 48 48 1 0 0 0 0 1 32 32 1 0 1 1 0 1 8 8 1 0 0 1 1 1 48 8 1 0 0 0 1 1 8 48 1 0 0 1 0 1 mclk = 16.9344 mhz sampling rate sampling - rate control settings adc dac filter type sampling rate control settings adc (khz) dac (khz) filter type sr3 sr2 sr1 sr0 bosr 88.2 88.2 2 1 1 1 1 1 44.1 44.1 1 1 0 0 0 1 8.021 8.021 1 1 0 1 1 1 44.1 8.021 1 1 0 0 1 1 8.021 44.1 1 1 0 1 0 1
3 ? 11 3.3.3 digital filter characteristics parameter test conditions min typ max unit adc filter characteristics ( ti dsp 250 f s mode operation ) passband 0.05 db 0.416 f s hz stopband ? 6 db 0.5 f s hz passband ripple 0.05 db stopband attenuation f > 0.584 f s ? 60 db adc filter characteristics ( ti dsp 272 f s and normal mode operation ) passband 0.05 db 0.4535 f s hz stopband ? 6 db 0.5 f s hz passband ripple 0.05 db stopband attenuation f > 0.5465 f s ? 60 db adc high-pass filter characteristics ? 3 db, f s = 44.1 khz 3.7 hz ? 3 db, f s = 48 khz 4.0 hz corner frequency ? 0.5 db, f s = 44.1 khz 10.4 hz corner frequency ? 0.5 db, f s = 48 khz 11.3 hz ? 0.1 db f s = 44.1 khz 21.6 hz ? 0.1 db, f s = 48 khz 23.5 hz dac filter characteristics (48-khz sampling rate) passband 0.03 db 0.416 f s hz stopband ? 6 db 0.5 f s hz passband ripple 0.03 db stopband attenuation f > 0.584 f s ? 50 db dac filter characteristics (44.1-khz sampling rate) passband 0.03 db 0.4535 f s hz stopband ? 6 db 0.5 fs hz passband ripple 0.03 db stopband attenuation f > 0.5465 f s ? 50 db
3 ? 12 ? 6 ? 8 ? 10 filter response ? db ? 4 ? 2 normalized audio sampling frequency 0 0 0.1 0.2 0.3 filter response vs normalized audio sampling frequency 0.4 0.5 figure 3 ? 9. digital de-emphasis filter response ? 44.1 khz sampling ? 6 ? 8 ? 10 0 0.10 0.20 0.30 filter response ? db ? 4 ? 2 normalized audio sampling frequency 0 0.40 0.50 filter response vs normalized audio sampling frequency figure 3 ? 10. digital de-emphasis filter response ? 48 khz sampling
3 ? 13 ? 70 ? 90 0 0.5 1 1.5 ? 50 ? 10 10 2 2.5 3 ? 30 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 11. adc digital filter response i: ti dsp and normal modes (group delay = 12 output samples) ? 0.04 ? 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.08 0.10 0.35 0.4 0.45 0.5 0.06 0.04 0.02 ? 0.02 ? 0.06 ? 0.08 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 12. adc digital filter ripple i: ti dsp and normal modes (group delay = 20 output samples)
3 ? 14 ? 50 ? 90 0 0.5 1 1.5 2 ? 30 ? 10 10 2.5 3 ? 70 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 13. adc digital filter response ii: ti dsp mode only ? 0.04 ? 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.08 0.10 0.35 0.4 0.45 0.5 0.06 0.04 0.02 ? 0.02 ? 0.06 ? 0.08 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 14. adc digital filter ripple ii: ti dsp mode only
3 ? 15 ? 70 ? 90 0 0.5 1 1.5 ? 50 ? 10 10 2 2.5 3 ? 30 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 15. adc digital filter response iii: ti dsp and normal modes (group delay = 3 output samples) ? 0.2 ? 0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.3 0.4 0.35 0.4 0.45 0.5 0.2 0.1 ? 0.1 ? 0.3 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 16. adc digital filter ripple iii: ti dsp and normal modes
3 ? 16 ? 50 ? 90 0 0.5 1 1.5 ? 30 ? 10 10 2 2.5 3 ? 70 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 17. adc digital filter response iv: ti dsp mode only ? 0.2 ? 0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0 0.3 0.4 0.35 0.40 0.45 0.50 0.2 0.1 ? 0.1 ? 0.3 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 18. adc digital filter ripple iv: ti dsp mode only
3 ? 17 ? 90 0 0.5 1 1.5 10 2 2.5 3 ? 10 ? 30 ? 50 ? 70 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 19. dac digital filter response i: ti dsp and normal modes ? 0.04 ? 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.08 0.10 0.35 0.4 0.45 0.5 0.06 0.04 0.02 ? 0.02 ? 0.06 ? 0.08 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 20. dac digital filter ripple i: ti dsp and normal modes
3 ? 18 ? 50 ? 90 0 0.5 1 1.5 ? 30 ? 10 10 2 2.5 3 ? 70 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 21. dac digital filter response ii: ti dsp mode only ? 0.04 ? 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.06 0.08 0.10 0.35 0.4 0.45 0.5 0.04 0.02 0 ? 0.02 ? 0.06 ? 0.08 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 22. dac digital filter ripple ii: ti dsp mode only
3 ? 19 ? 50 ? 90 0 0.5 1 1.5 ? 30 ? 10 10 2 2.5 3 ? 70 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 23. dac digital filter response iii: ti dsp and normal modes ? 0.2 ? 0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.2 0.3 0.4 0.35 0.4 0.45 0.5 0.1 0 ? 0.1 ? 0.3 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 24. dac digital filter ripple iii: ti dsp and normal modes
3 ? 20 ? 70 ? 90 0 0.5 1 1.5 ? 30 ? 10 10 2 2.5 3 ? 50 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 25. dac digital filter response iv: ti dsp mode only ? 0.2 ? 0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.3 0.4 0.35 0.4 0.45 0.5 0.2 0.1 ? 0.1 ? 0.3 filter response ? db normalized audio sampling frequency filter response vs normalized audio sampling frequency figure 3 ? 26. dac digital filter ripple iv: ti dsp mode only
a ? 1 appendix a mechanical data gqe (s-pbga-n80) plastic ball grid array 9 8 7 6 5 j h g f e d 3 2 1 c b a 4 4,00 typ 5,10 4,90 sq 0,50 0,50 4200461/c 10/00 seating plane 0,62 0,68 0,25 0,35 1,00 max 0,08 m ? 0,05 0,11 0,21 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar junior ? bga configuration d. falls within jedec mo-225 microstar junior is a trademark of texas instruments.
a ? 2 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 ? 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153

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